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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 dacx1408 8-channel, 16-,14-,12-bit, high-voltage output dacs with internal reference 1 1 features 1 ? performance ? specified monotonic at 16-bit resolution ? inl: 1 lsb maximum at 16-bit resolution ? tue: 0.1% of fsr maximum ? integrated 2.5-v precision internal reference ? initial accuracy: 2.5 mv maximum ? low drift: 5 ppm/ ? c typical ? flexible output configuration ? output range: 2.5 v, 5 v, 10 v, 20 v 0 to 5 v, 0 to 10 v, 0 to 20 v, 0 to 40 v ? differential output mode ? high drive capability: 25 ma with 1.5 v from supply rails ? three dedicated a-b toggle pins for dither signal generation ? analog temperature output ? sensor gain of ? 4 mv/ ? c ? 50-mhz spi compatible serial interface ? 4-wire mode, 1.7-v to 5.5-v operation ? daisy chain operation ? crc error check ? temperature range: ? 40 ? c to +125 ? c ? small package ? 6 mm 6 mm, 40-pin vqfn 2 applications ? optical networking: mach-zehnder modulator bias control ? industrial automation ? test and measurement 3 description the dac81408, dac71408, and dac61408 (dacx1408) are a pin-compatible family of 8-channel, buffered, high-voltage output digital-to-analog converters (dacs) with 16-, 14- and 12-bit resolution. the dacx1408 includes a low drift, 2.5-v internal reference, eliminating the need for an external precision reference in most applications. these devices are specified monotonic and provide high linearity of 1 lsb inl. a user selectable output configuration enables full- scale bipolar output voltages: 20 v, 10 v, 5 v or 2.5 v and full-scale unipolar output voltages: 40 v, 20 v, 10 v or 5 v. the full-scale output range for each dac channel is independently programmable. the integrated dac output buffers can sink or source up to 25 ma thus limiting the need of additional operational amplifiers. each pair of channels can be configured to provide a differential output with offset calibration. the three dedicated a-b toggle pins enable dither signal generation with up to three possible frequencies. the dacx1408 incorporates a power-on-reset circuit that connects the dac outputs to ground at power- up. the outputs remain at this state until the device registers are properly configured for operation. communication to the dacx1408 is performed through a 4-wire serial interface that supports operation from 1.7 v to 5.5 v. device information (1) part number package body size (nom) dac81408 dac71408 dac61408 vqfn (40) 6.00 mm 6.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. functional block diagram productfolder dacx140 8 chann el 0 buf out0 dac chann el 1 power down logic resistive network digital interface power on reset out1 ref sclk sdi sdo vss vdd cs inte rnal reference vio chann el 7 ldac reset clr almout vcc refgnd range config gnd out7 temperature sen sor tempout refcmp dac buffer dac registe r toggl e0 vaa toggl e1 toggl e2 support &community tools & software technical documents ordernow
2 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 device comparison table ..................................... 3 6 pin configuration and functions ......................... 3 7 specifications ......................................................... 5 7.1 absolute maximum ratings ...................................... 5 7.2 esd ratings .............................................................. 5 7.3 recommended operating conditions ....................... 5 7.4 thermal information .................................................. 6 7.5 electrical characteristics ........................................... 7 7.6 timing requirements .............................................. 11 7.7 typical characteristics ............................................ 13 8 parameter measurement information ................ 21 9 detailed description ............................................ 22 9.1 overview ................................................................. 22 9.2 functional block diagram ....................................... 22 9.3 feature description ................................................. 23 9.4 device functional modes ........................................ 26 9.5 programming ........................................................... 28 9.6 register maps ......................................................... 31 10 application and implementation ........................ 46 10.1 application information .......................................... 46 10.2 typical application ............................................... 46 11 power supply recommendations ..................... 49 12 layout ................................................................... 50 12.1 layout guidelines ................................................. 50 12.2 layout example .................................................... 50 13 device and documentation support ................. 51 13.1 documentation support ....................................... 51 13.2 related links ........................................................ 51 13.3 receiving notification of documentation updates 51 13.4 community resources .......................................... 51 13.5 trademarks ........................................................... 51 13.6 electrostatic discharge caution ............................ 51 13.7 glossary ................................................................ 51 14 mechanical, packaging, and orderable information ........................................................... 51 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from original (july 2018) to revision a page ? changed dac81408 from advance information to production data ..................................................................................... 1 ? changed dac71408 and dac61408 from product preview to production data .................................................................. 1
3 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 device comparison table device resolution dac81408 16-bit dac71408 14-bit dac61408 12-bit 6 pin configuration and functions rha package 40-pin vqfn top view 40 vcc 11 sdo 1 nc 30 nc 39 vss 12 sclk 2 nc 29 nc 38 vdd 13 sdi 3 nc 28 nc 37 vaa 14 cs 4 nc 27 nc 36 gnd 15 toggle0 5 out0 26 out7 35 refgnd 16 toggle1 6 out1 25 out6 34 refcmp 17 toggle2 7 out2 24 out5 33 ref 18 ldac 8 out3 23 out4 32 vss 19 reset 9 vio 22 tempout 31 vcc 20 clr 10 gnd 21 almout not to scale thermal pad
4 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions pin type description name no. out[0:7] 5 - 8, 23 - 26 o analog dac output voltages. nc 1, 2, 3, 4, 27, 28, 29, 30 o no connection. vio 9 pwr io supply voltage. (1.7 v to 5.5 v). this pin sets the i/o operating voltage for the device. gnd 10, 36 gnd ground reference point for all circuitry on the device. sdo 11 o serial interface data output. the sdo pin must be enabled before operation by setting the sdo-en bit. data are clocked out of the input shift register on either rising or falling edges of the sclk pin as specified by the fsdo bit (rising edge by default). sclk 12 i serial interface clock. sdi 13 i serial interface data input. data are clocked into the input shift register on each falling edge of the sclk pin. cs 14 i active low serial data enable. this input is the frame synchronization signal for the serial data. when the signal goes low, it enables the serial interface input shift register. toggle0 15 i toggle pins. control signals for those dac outputs configured for toggle operation to switch between the two dac data registers associated with each dac. a logic low updates the dac output to the value set by register a. a logic high updates the dac output to the value set by register b. connect the toggle pins to ground if not using the toggle operation. toggle1 16 i toggle2 17 i ldac 18 i active low synchronization signal. when the ldac pin is low, the dac outputs of those channels configured in synchronous mode are updated simultaneously. connect to vio if unused. reset 19 i active low reset input. logic low on this pin causes the device to issue a power-on-reset event. clr 20 i active low clear input. logic low on this pin clears all dac outputs to their clear code. connect to vio if unused. almout 21 o almout is an open drain alarm output. an external 10-k ? pull-up resistor to a voltage no higher than v io is required. tempout 22 o analog temperature monitor output. vcc 31, 40 pwr output positive analog power supply (9 v to 41.5 v). vss 32, 39 pwr output negative analog power supply (-21.5 v to 0 v). ref 33 i/o reference input to the device when operating with external reference. when using internal reference, this is the reference output voltage pin. connect a 150-nf capacitor to ground. refcmp 34 i/o reference compensation capacitor connection. connect a 330-pf capacitor between refcmp and refgnd. refgnd 35 gnd ground reference point for the internal reference. vaa 37 pwr analog supply voltage (4.5 v to 5.5 v). this pin must be at the same potential as the vdd pin. vdd 38 pwr digital supply voltage (4.5 v to 5.5 v). this pin must be at the same potential as the vaa pin. thermal pad ? ? the thermal pad is located on the package underside. the thermal pad should be connected to any internal pcb ground plane through multiple vias for good thermal performance.
5 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage v dd to gnd -0.3 6 v v io to gnd -0.3 6 v v cc to gnd -0.3 44 v v ss to gnd -22 0.3 v refgnd to gnd -0.3 0.9 v v dd to v aa -0.3 0.3 v v cc to v ss -0.3 44 v pin voltage dac outputs to gnd v ss - 0.3 v cc + 0.3 v tempout to gnd -0.3 v dd + 0.3 v ref and refcmp to gnd -0.3 v dd + 0.3 v digital inputs to gnd -0.3 v io + 0.3 v sdo to gnd -0.3 v io + 0.3 v alarmout to gnd -0.3 6 v operating junction temperature, t j -40 150 c storage temperature, t stg -60 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001 (1) 1000 v charged device model (cdm), per jedec specification jesd22-c101 (2) 500 (1) v aa and v dd must be at the same potential. (2) v ss is only connected to gnd when all dac outputs are unipolar. (3) if v refgnd is not connected to gnd, a buffered source must be used to drive it. 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v aa (1) 4.5 5.5 v v dd (1) 4.5 5.5 v v io 1.7 5.5 v v cc 9 41.5 v v ss (2) -21.5 0 v v cc ? v ss 9 43 v digital input voltage 0 v io v v refin reference input voltage to v refgnd 2.49 2.5 2.51 v v refgnd (3) refgnd pin voltage 0 0 0.6 v t a operating ambient temperature -40 125 c
6 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953. 7.4 thermal information thermal metric (1) dacx1408 rha (vqfn) 40 pins r ja junction-to-ambient thermal resistance 26.8 r jc(top) junction-to-case (top) thermal resistance 14.1 r jb junction-to-board thermal resistance 3.4 jt junction-to-top characterization parameter 0.2 jb junction-to-board characterization parameter 3.4 r jc(bot) junction-to-case (bottom) thermal resistance 0.7
7 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) end point fit between codes. 16-bit: code 256 to 65280, 14-bit: code 128 to 16256, 12-bit: code 32 to 4064. (2) temporary overload condition protection. junction temperature can be exceeded during current limit. operation above the specified maximum junction temperature may impair device reliability. (3) specified by design and characterization, not production tested. 7.5 electrical characteristics all minimum/maximum specifications at t a = -40 to +125 and all typical specifications at t a = 25 , v cc = 9 v to 41.5 v, v ss = -21.5 v to 0 v, v dd = v aa = 4.5 v to 5.5 v, v refin = 2.5 v, v io = 1.7 v to 5.5 v, dac outputs unloaded, digital inputs at v io or gnd (unless otherwise noted) parameter test conditions min typ max unit static performance (1) dac81408 resolution 16 bits integral nonlinearity (inl) all ranges, except 0 to 40 v and 2.5 v -1 0.5 1 lsb 0 to 40 v and 2.5 v range -2 1 2 lsb differential nonlinearity (dnl) specified 16-bit monotonic -1 0.5 1 lsb dac71408 resolution 14 bits integral nonlinearity (inl) all ranges -1 0.5 1 lsb differential nonlinearity (dnl) specified 14-bit monotonic -1 0.5 1 lsb dac61408 resolution 12 bits integral nonlinearity (inl) all ranges -1 0.5 1 lsb differential nonlinearity (dnl) specified 12-bit monotonic -1 0.5 1 lsb tue total unadjusted error all ranges, except 2.5 v -0.1 0.01 0.1 %fsr 2.5 v range -0.2 0.02 0.2 unipolar offset error all unipolar ranges -0.03 0.015 0.03 %fsr unipolar zero-code error all unipolar ranges 0 0.04 0.1 %fsr bipolar zero error all bipolar ranges -0.2 0.02 0.2 %fsr full-scale error all ranges -0.2 0.075 0.2 %fsr gain error all ranges, except 2.5 v -0.1 0.02 0.1 %fsr 2.5 v range -0.2 0.02 0.2 unipolar offset error drift all unipolar ranges 2 ppm of fsr/ c bipolar zero error drift all bipolar ranges 2 ppm of fsr/ c gain error drift all ranges 2 ppm of fsr/ c output voltage drift over time t a = 40 c, full-scale code, 1900 hours 5 ppm of fsr differential mode performance (1) tue total unadjusted error all ranges -0.1 0.01 0.1 %fsr 2.5 v range -0.2 0.02 0.2 common mode error all bipolar ranges. midscale code -0.1 0.01 0.1 %fsr output characteristics output voltage headroom to v ss and v cc (-10 ma i out 10 ma) 1 v to v ss and v cc (-15 ma i out 15 ma) 1.5 short circuit current (2) full-scale output shorted to v ss 40 ma zero-scale output shorted to v cc 40 load regulation midscale code, -15 ma i out 15 ma 70 v/ma maximum capacitive load (3) r load = open 0 1 nf dc output impedance midscale code 0.05 full-scale code 40
8 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) all minimum/maximum specifications at t a = -40 to +125 and all typical specifications at t a = 25 , v cc = 9 v to 41.5 v, v ss = -21.5 v to 0 v, v dd = v aa = 4.5 v to 5.5 v, v refin = 2.5 v, v io = 1.7 v to 5.5 v, dac outputs unloaded, digital inputs at v io or gnd (unless otherwise noted) parameter test conditions min typ max unit dynamic performance output voltage settling time ? to ? scale and ? to ? scale settling time to 1 lsb, 10 v range, r l = 5 k , c l = 200 pf 12 s slew rate 0 to 5 v range 1 v/ s all other output ranges 4 power-on glitch magnitude power-down to active dac output. 20 v range, midscale code, r l = 5 k , c l = 200 pf 0.3 v output noise 0.1 hz to 10 hz, midscale code, 0 to 5 v range 15 vpp output noise density 1 khz, midscale code, 0 to 5 v range 78 nv/hz ac psrr midscale code, frequency = 60 hz, amplitude 200 mvpp superimposed on v dd , v cc or v ss 1 lsb/v dc psrr midscale code, v dd = 5 v 5%, v cc = 20 v, v ss = -20 v 1 lsb/v midscale code, v dd = 5 v, v cc = 20 v 5%, v ss = -20 v 1 midscale code, v dd = 5 v, v cc = 20 v, v ss = -20 v 5% 1 code change glitch impulse 1 lsb change around major carrier, 0 to 5 v range 4 nv-s channel to channel ac crosstalk 0 to 5 v range. measured channel at midscale. full-scale swing on all other channels 4 nv-s channel to channel dc crosstalk 0 to 5 v range. measured channel at midscale. all other channels at full- scale 0.25 lsb digital feedthrough 0 to 5 v range. midscale code, f sclk = 1 mhz 1 nv-s
9 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) all minimum/maximum specifications at t a = -40 to +125 and all typical specifications at t a = 25 , v cc = 9 v to 41.5 v, v ss = -21.5 v to 0 v, v dd = v aa = 4.5 v to 5.5 v, v refin = 2.5 v, v io = 1.7 v to 5.5 v, dac outputs unloaded, digital inputs at v io or gnd (unless otherwise noted) parameter test conditions min typ max unit external reference input v refin reference input voltage range to v refgnd 2.49 2.5 2.51 v reference input current 50 a reference input impedance 50 k reference input capacitance 20 pf internal reference v refout reference output voltage range t a = 25 c 2.4975 2.5025 v reference output drift 5 15 ppm/ c reference output impedance 0.1 reference output noise 0.1 hz to 10 hz 12 vpp reference output noise density 10 khz, ref load = 10 nf 150 nv/hz reference load current 5 ma reference load regulation source 80 v/ma reference line regulation 20 v/v reference output drift over time t a = 25 c, 1900 hours 250 v reference thermal hysteresis first cycle 700 v additional cycle 50 digital inputs and outputs v ih high-level input voltage 0.7 v io v v il low-level input voltage 0.3 v io v input current 2 a input pin capacitance 2 pf v oh high-level output voltage i oh = 0.2 ma v io - 0.2 v v ol low-level output voltage i ol = 0.2 ma 0.4 v output pin capacitance 5 pf alarm output output pin capacitance 5 pf v ol low-level output voltage i load = -0.2 ma 0.4 v temperature output v tempout,0c output voltage offset at 0 1.34 v sensor gain -4 mv/ c
10 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) all minimum/maximum specifications at t a = -40 to +125 and all typical specifications at t a = 25 , v cc = 9 v to 41.5 v, v ss = -21.5 v to 0 v, v dd = v aa = 4.5 v to 5.5 v, v refin = 2.5 v, v io = 1.7 v to 5.5 v, dac outputs unloaded, digital inputs at v io or gnd (unless otherwise noted) parameter test conditions min typ max unit power requirements i dd v dd supply current active mode. internal reference enabled. full-scale code. 20 v output range. spi static. 0.05 0.5 ma active mode. internal reference disabled. full-scale code. 20 v output range. spi static. 0.05 0.5 ma power-down mode 0.05 0.5 ma i aa v aa supply current active mode. internal reference enabled. full-scale code. 20 v output range. spi static. 20 30 ma active mode. internal reference disabled. full-scale code. 20 v output range. spi static. 18 28 ma power-down mode 2 85 a i cc v cc supply current active mode. internal reference enabled. full-scale code. 20 v output range. spi static. 5 10 ma active mode. internal reference disabled. full-scale code. 20 v output range. spi static. 5 10 ma power-down mode 10 30 a i ss v ss supply current active mode. internal reference enabled. full-scale code. 20 v output range. spi static. -10 -5 ma active mode. internal reference disabled. full-scale code. 20 v output range. spi static. -10 -5 ma power-down mode -30 -10 a i io v io supply current sclk and sdi toggling at 50 mhz 350 500 a
11 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6 timing requirements over operating free-air temperature range (unless otherwise noted) min nom max unit serial interface - write operation f (sclk) serial clock frequency v io = 1.7 v to 2.7 v 25 mhz v io = 2.7 v to 5.5 v 50 t sclkhigh sclk high time v io = 1.7 v to 2.7 v 20 ns v io = 2.7 v to 5.5 v 10 t sclklow sclk low time v io = 1.7 v to 2.7 v 20 ns v io = 2.7 v to 5.5 v 10 t sdis sdi setup time v io = 1.7 v to 2.7 v 10 ns v io = 2.7 v to 5.5 v 5 t sdih sdi hold time v io = 1.7 v to 2.7 v 10 ns v io = 2.7 v to 5.5 v 5 t css cs to sclk falling edge setup time v io = 1.7 v to 2.7 v 30 ns v io = 2.7 v to 5.5 v 15 t csh sclk falling edge to cs rising edge v io = 1.7 v to 2.7 v 10 ns v io = 2.7 v to 5.5 v 5 t cshigh cs hight time v io = 1.7 v to 2.7 v 50 ns v io = 2.7 v to 5.5 v 25 t dacwait sequential dac update wait time v io = 1.7 v to 2.7 v 2.4 s v io = 2.7 v to 5.5 v 2.4 t bcastwait broadcast dac update wait time v io = 1.7 v to 2.7 v 4 s v io = 2.7 v to 5.5 v 4 serial interface - read and daisy chain operation, fsdo = 0 f (sclk) serial clock frequency v io = 1.7 v to 2.7 v 15 mhz v io = 2.7 v to 5.5 v 20 t sclkhigh sclk high time v io = 1.7 v to 2.7 v 33 ns v io = 2.7 v to 5.5 v 25 t sclklow sclk low time v io = 1.7 v to 2.7 v 33 ns v io = 2.7 v to 5.5 v 25 t sdis sdi setup time v io = 1.7 v to 2.7 v 10 ns v io = 2.7 v to 5.5 v 5 t sdih sdi hold time v io = 1.7 v to 2.7 v 10 ns v io = 2.7 v to 5.5 v 5 t css cs to sclk falling edge setup time v io = 1.7 v to 2.7 v 30 ns v io = 2.7 v to 5.5 v 20 t csh sclk falling edge to cs rising edge v io = 1.7 v to 2.7 v 8 ns v io = 2.7 v to 5.5 v 5 t cshigh cs high time v io = 1.7 v to 2.7 v 50 ns v io = 2.7 v to 5.5 v 25 t sdozd sdo tri-state to driven v io = 1.7 v to 2.7 v 0 20 ns v io = 2.7 v to 5.5 v 0 20 t sdodly sdo output delay v io = 1.7 v to 2.7 v 0 35 ns v io = 2.7 v to 5.5 v 0 20
12 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated timing requirements (continued) over operating free-air temperature range (unless otherwise noted) min nom max unit serial interface - read and daisy chain operation, fsdo = 1 f (sclk) serial clock frequency v io = 1.7 v to 2.7 v 25 mhz v io = 2.7 v to 5.5 v 35 t sclkhigh sclk high time v io = 1.7 v to 2.7 v 20 ns v io = 2.7 v to 5.5 v 14 t sclklow sclk low time v io = 1.7 v to 2.7 v 20 ns v io = 2.7 v to 5.5 v 14 t sdis sdi setup time v io = 1.7 v to 2.7 v 10 ns v io = 2.7 v to 5.5 v 5 t sdih sdi hold time v io = 1.7 v to 2.7 v 10 ns v io = 2.7 v to 5.5 v 5 t css cs to sclk falling edge setup time v io = 1.7 v to 2.7 v 30 ns v io = 2.7 v to 5.5 v 20 t csh sclk falling edge to cs rising edge v io = 1.7 v to 2.7 v 8 ns v io = 2.7 v to 5.5 v 5 t cshigh cs high time v io = 1.7 v to 2.7 v 50 ns v io = 2.7 v to 5.5 v 25 t sdozd sdo tri-state to driven v io = 1.7 v to 2.7 v 0 20 ns v io = 2.7 v to 5.5 v 0 20 t sdodly sdo output delay v io = 1.7 v to 2.7 v 0 35 ns v io = 2.7 v to 5.5 v 0 20 digital logic t logdly cs rising edge to ldac or clr falling edge delay time v io = 1.7 v to 2.7 v 40 ns t logdly cs rising edge to ldac or clr falling edge delay time v io = 2.7 v to 5.5 v 20 t ldac ldac low time v io = 1.7 v to 2.7 v 20 ns v io = 2.7 v to 5.5 v 10 t clr clr low time v io = 1.7 v to 2.7 v 20 ns v io = 2.7 v to 5.5 v 10 t reset por reset delay v io = 1.7 v to 2.7 v 1 ms v io = 2.7 v to 5.5 v 1 f toggle toggle frequency v io = 1.7 v to 2.7 v 100 khz v io = 2.7 v to 5.5 v 100
13 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.7 typical characteristics at t a = 25 c, v dd = v aa = 5 v, v refin = 2.5 v. unipolar ranges: v ss = 0 v and v cc v max + 1.5 v for the dac range. bipolar ranges: v ss v min ? 1.5 v and v cc v max + 1.5 v for the dac range. dac outputs unloaded, unless otherwise noted. figure 1. integral linearity error vs digital input code (bipolar outputs) figure 2. integral linearity error vs digital input code (unipolar outputs) figure 3. differential linearity error vs digital input code (bipolar outputs) figure 4. differential linearity error vs digital input code (unipolar outputs) figure 5. total unadjusted error vs digital input code (bipolar outputs) figure 6. total unadjusted error vs digital input code (unipolar outputs) code inl (lsb) 0 8192 16384 24576 32768 40960 49152 57344 65536 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 d002 0-5v 0-10 v 0-20 v 0-40 v code dnl (lsb) 0 8192 16384 24576 32768 40960 49152 57344 65536 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 d004 0-5v 0-10 v 0-20 v 0-40 v code inl (lsb) 0 8192 16384 24576 32768 40960 49152 57344 65536 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 d001 2.5v 5v 10v 20v code tue (%fsr) 0 8192 16384 24576 32768 40960 49152 57344 65536 -0.100 -0.075 -0.050 -0.025 0.000 0.025 0.050 0.075 0.100 d005 2.5v 5v 10v 20v code dnl (lsb) 0 8192 16384 24576 32768 40960 49152 57344 65536 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 d003 2.5v 5v 10v 20v code tue (%fsr) 0 8192 16384 24576 32768 40960 49152 57344 65536 -0.100 -0.075 -0.050 -0.025 0.000 0.025 0.050 0.075 0.100 d006 0-5v 0-10 v 0-20 v 0-40 v
14 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v dd = v aa = 5 v, v refin = 2.5 v. unipolar ranges: v ss = 0 v and v cc v max + 1.5 v for the dac range. bipolar ranges: v ss v min ? 1.5 v and v cc v max + 1.5 v for the dac range. dac outputs unloaded, unless otherwise noted. figure 7. common mode error vs digital input code (differential bipolar outputs) figure 8. common mode error vs digital input code (differential unipolar outputs) 20-v output range figure 9. integral linearity error vs temperature 20-v output range figure 10. differential linearity error vs temperature figure 11. total unadjusted error vs temperature figure 12. unipolar offset error vs temperature temperature ( o c) unipolar offset error (%fsr) -40 -25 -10 5 20 35 50 65 80 95 110 125 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 d012 0-5 v 0-10 v 0-20 v 0-40 v temperature ( o c) inl (lsb) -40 -25 -10 5 20 35 50 65 80 95 110 125 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 d009 inl max inl min temperature ( o c) tue (%fsr) -40 -25 -10 5 20 35 50 65 80 95 110 125 -0.100 -0.075 -0.050 -0.025 0.000 0.025 0.050 0.075 0.100 d011 0-5 v 0-10 v 0-20 v 0-40 v 2.5 v 5 v 10 v 20 v code common mode error (%fsr) 0 8192 16384 24576 32768 40960 49152 57344 65536 -0.0500 -0.0375 -0.0250 -0.0125 0.0000 0.0125 0.0250 0.0375 0.0500 d008 0-5 v 0-10 v 0-20 v 0-40 v code common mode error (%fsr) 0 8192 16384 24576 32768 40960 49152 57344 65536 -0.0500 -0.0375 -0.0250 -0.0125 0.0000 0.0125 0.0250 0.0375 0.0500 d007 2.5v 5v 10v 20v temperature ( o c) dnl (lsb) -40 -25 -10 5 20 35 50 65 80 95 110 125 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 d010 dnl max dnl min
15 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v dd = v aa = 5 v, v refin = 2.5 v. unipolar ranges: v ss = 0 v and v cc v max + 1.5 v for the dac range. bipolar ranges: v ss v min ? 1.5 v and v cc v max + 1.5 v for the dac range. dac outputs unloaded, unless otherwise noted. figure 13. unipolar zero code error vs temperature figure 14. bipolar zero error vs temperature figure 15. gain error vs temperature figure 16. full-scale error vs temperature figure 17. common mode error vs temperature (differential bipolar outputs) figure 18. common mode error vs temperature (differential unipolar outputs) temperature ( o c) full scale error (%fsr) -40 -25 -10 5 20 35 50 65 80 95 110 125 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 d016 2.5 v 5 v 10 v 20 v 0-5 v 0-10 v 0-20 v 0-40 v temperature ( o c) common mode error (%fsr) -40 -25 -10 5 20 35 50 65 80 95 110 125 -0.0500 -0.0375 -0.0250 -0.0125 0.0000 0.0125 0.0250 0.0375 0.0500 d018 0-5 v 0-10 v 0-20 v 0-40 v temperature ( o c) gain error (%fsr) -40 -25 -10 5 20 35 50 65 80 95 110 125 -0.100 -0.075 -0.050 -0.025 0.000 0.025 0.050 0.075 0.100 d015 2.5 v 5 v 10 v 20 v 0-5 v 0-10 v 0-20 v 0-40 v temperature ( o c) common mode error (%fsr) -40 -25 -10 5 20 35 50 65 80 95 110 125 -0.0500 -0.0375 -0.0250 -0.0125 0.0000 0.0125 0.0250 0.0375 0.0500 d017 2.5 v 5 v 10 v 20 v temperature ( o c) bipolar zero error (%fsr) -40 -25 -10 5 20 35 50 65 80 95 110 125 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 d014 2.5 v 5 v 10 v 20 v temperature ( o c) unipolar zero code error (%fsr) -40 -25 -10 5 20 35 50 65 80 95 110 125 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 d013 0-5 v 0-10 v 0-20 v 0-40 v
16 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v dd = v aa = 5 v, v refin = 2.5 v. unipolar ranges: v ss = 0 v and v cc v max + 1.5 v for the dac range. bipolar ranges: v ss v min ? 1.5 v and v cc v max + 1.5 v for the dac range. dac outputs unloaded, unless otherwise noted. 20-v output range figure 19. supply current (i dd , i aa ) vs digital input code 20-v output range figure 20. supply current (i cc , i ss ) vs digital input code 20-v output range figure 21. supply current (i io ) vs supply voltage 20-v output range figure 22. supply current vs temperature 20-v output range figure 23. power-down current vs temperature 20-v output range figure 24. source and sink capability load current (ma) dac output (v) -50 -40 -30 -20 -10 0 10 20 30 40 50 -40 -30 -20 -10 0 10 20 30 40 d024 code 0x0000 code 0x8000 code 0xffff v io (v) i io ( p a) 1.7 2.65 3.6 4.55 5.5 0 50 100 150 200 250 300 350 400 450 500 d021 temperature ( o c) supply current (ma) -40 -25 -10 5 20 35 50 65 80 95 110 125 -25 -20 -15 -10 -5 0 5 10 15 20 25 d022 i dd i aa i cc i ss code i dd ( p$ ) i aa (ma) 0 8192 16384 24576 32768 40960 49152 57344 65536 0 0 5 5 10 10 15 15 20 20 25 25 30 30 d019 i dd i aa code i cc , i ss (ma) 0 8192 16384 24576 32768 40960 49152 57344 65536 -25 -20 -15 -10 -5 0 5 10 15 20 25 d020 i cc i ss temperature ( o c) supply current ( p a) -40 -25 -10 5 20 35 50 65 80 95 110 125 -30 -15 0 15 30 45 60 75 90 d023 i dd i aa i cc i ss
17 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v dd = v aa = 5 v, v refin = 2.5 v. unipolar ranges: v ss = 0 v and v cc v max + 1.5 v for the dac range. bipolar ranges: v ss v min ? 1.5 v and v cc v max + 1.5 v for the dac range. dac outputs unloaded, unless otherwise noted. full-scale code figure 25. v cc headroom vs sourcing current zero code figure 26. v ss footroom vs sinking current 20-v output range figure 27. full-scale settling time, rising edge 20-v output range figure 28. full-scale settling time, falling edge power-down to active dac mode 20-v output range figure 29. dac output enable glitch 0 to 5-v output range figure 30. glitch impulse, 1 lsb step sinking current (ma) footroom (v) 0 3 6 9 12 15 18 21 24 27 30 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 d026 20 v 10 v time (5 p sec/div) v out (v) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 d029 sourcing current (ma) headroom (v) 0 3 6 9 12 15 18 21 24 27 30 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 d025 20 v 10 v time (5 p sec/div) d028 ldac (5v/div) v out (5v/div) time (5 p sec/div) d027 ldac (5v/div) v out (5v/div) time (0.5 p sec/div) d030 ldac (5v/div) v out (5mv/div)
18 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v dd = v aa = 5 v, v refin = 2.5 v. unipolar ranges: v ss = 0 v and v cc v max + 1.5 v for the dac range. bipolar ranges: v ss v min ? 1.5 v and v cc v max + 1.5 v for the dac range. dac outputs unloaded, unless otherwise noted. 20-v output range toggle signal: 1 v pp dc change: midscale to 3/4 full-scale figure 31. toggle output change response 20-v output range toggle signal: 1 v pp dc value: 3/4 full-scale figure 32. toggle enable response figure 33. power-up response figure 34. power-down response 20-v output range full-scale code to 0 v figure 35. clear command response 20-v output range toggle signal: 1 v pp dc value at 20 v figure 36. clear command response in toggle mode time (1 msec/div) d035 clr (5 v/div) v out (5 v/div) time (0.5 msec/div) d036 clr (5 v/div) v out (5 v/div) time (25 p sec/div) v out (v) -5 0 5 10 15 20 d031 time (25 p sec/div) v out (v) -5 0 5 10 15 20 d032 time (50 msec/div) voltage (5 v/div) d033 v out v cc v ss v dd = v aa = v io time (50 msec/div) voltage (5 v/div) d034 v out v cc v ss v dd = v aa = v io
19 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v dd = v aa = 5 v, v refin = 2.5 v. unipolar ranges: v ss = 0 v and v cc v max + 1.5 v for the dac range. bipolar ranges: v ss v min ? 1.5 v and v cc v max + 1.5 v for the dac range. dac outputs unloaded, unless otherwise noted. 0 to 5-v output range midscale code figure 37. dac output noise density vs frequency 0 to 5-v output range midscale code figure 38. dac output noise figure 39. internal reference voltage vs temperature figure 40. internal reference voltage vs supply voltage figure 41. internal reference voltage vs time figure 42. internal reference noise density vs frequency v dd , v aa (v) internal reference (v) 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 2.4995 2.4996 2.4997 2.4998 2.4999 2.5000 2.5001 2.5002 2.5003 2.5004 2.5005 d040 frequency (hz) noise (nv/ ? hz) 100 1000 10000 100000 0 150 300 450 600 750 900 1050 1200 1350 1500 d037 time (1 sec/div) v noise (5 p v/div) d038 frequency (hz) noise (nv/ ? hz) 100 1000 10000 100000 0 150 300 450 600 750 900 1050 1200 1350 1500 d042 hours internal reference (v) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2.4995 2.4996 2.4997 2.4998 2.4999 2.5000 2.5001 2.5002 2.5003 2.5004 2.5005 d041 temperature ( o c) internal reference (v) -40 -25 -10 5 20 35 50 65 80 95 110 125 2.495 2.496 2.497 2.498 2.499 2.500 2.501 2.502 2.503 2.504 2.505 d039
20 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v dd = v aa = 5 v, v refin = 2.5 v. unipolar ranges: v ss = 0 v and v cc v max + 1.5 v for the dac range. bipolar ranges: v ss v min ? 1.5 v and v cc v max + 1.5 v for the dac range. dac outputs unloaded, unless otherwise noted. figure 43. internal reference noise figure 44. internal reference temperature drift histogram time (1 sec/div) v noise (5 p v/div) d043 temperature drift (ppm/ o c) percentage of units 0 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 0 1 2 3 4 5 6 7 8 9 10 d044
21 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 parameter measurement information figure 45. serial interface write timing diagram figure 46. serial interface read timing diagram bit 22 bit 0 t csh bit 23 bit 1 bit 0 sdo fsdo = 0 bit 23 bit 1 bit 0 t sdod z t sdod ly first re ad command t css t sdis t sdih cs sdi t csh igh bit 23 sclk sdo fsdo = 1 bit 23 bit 1 bit 0 t sdod ly any comma nd data from first read co mmand data from first read co mmand t scl khigh t scl klow t css t sdis t sdih cs sdi t csh igh bit 23 t scl klow bit 1 bit 0 t csh sclk t scl khigh
22 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 detailed description 9.1 overview the dacx1408 is a pin-compatible family of 8-channel, buffered, high-voltage output digital-to-analog converters (dacs) with 16-, 14- and 12-bit resolution. the dacx1408 includes a 2.5-v internal reference. a user selectable output configuration enables full-scale bipolar output voltages: 20 v, 10 v, 5 v or 2.5 v and full-scale unipolar output voltages: 40 v, 20 v, 10 v or 5 v. the full-scale output range for each dac channel is independently programmable. in addition, each pair of dac channels can be configured to provide a differential output. three dedicated a-b toggle pins enable dither signal generation with up to three possible frequencies. the dacx1408 operates from five supply voltages: v dd , v aa , v cc , v ss and v io . v dd and v aa are the digital and analog supplies for the dacs, internal reference and other low voltage components and must be set at the same potential. v cc and v ss are the positive and analog supplies for the dac output amplifiers. v io sets the logic levels for the digital inputs and outputs. communication to the dacx1408 is performed through a 4-wire serial interface that supports stand-alone and daisy-chain operation. the optional frame-error checking provides added robustness to the dacx1408 serial interface. the dacx1408 incorporates a power-on-reset circuit that connects the dac outputs to ground at power-up. the outputs remain at this state until the device registers are properly configured for operation. 9.2 functional block diagram dacx140 8 chann el 0 buf out0 dac chann el 1 power down logic resistive network digital interface power on reset out1 ref sclk sdi sdo vss vdd cs inte rnal reference vio chann el 7 ldac reset clr almout vcc refgnd range config gnd out7 temperature sen sor tempout refcmp dac buffer dac registe r toggl e0 vaa toggl e1 toggl e2
23 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.3 feature description 9.3.1 digital-to-analog converters (dacs) architecture each output channel in the dacx1408 consists of an r-2r ladder architecture followed by an output buffer amplifier capable of rail-to-rail operation. the output amplifiers can drive 25 ma with 1.5-v headroom from either v cc or v ss while maintaining the specified tue specification for the device. the full-scale output voltage for each channel can be individually configured to the following ranges: ? -20 v to +20 v ? -10 v to +10 v ? -5 v to +5 v ? -2.5 v to +2.5 v ? 0 v to +40v ? 0 v to +20 v ? 0 v to +10 v ? 0 v to +5 v figure 47 shows a block diagram of the dac architecture. figure 47. dacx1408 dac block diagram 9.3.1.1 dac transfer function the input data are written to the individual dac data registers in straight binary format for all output ranges. the dac transfer function is given by equation 1 . (1) where ? code is the decimal equivalent of the binary code that is loaded to the dac register. code range is from 0 to 2 n ? 1. ? n is the dac resolution in bits. either 12 (dac61408), 14 (dac71408) or 16 (dac81408). ? fsr is the dac full-scale range. equal to v max ? v min for the selected dac output range. ? v min is the lowest voltage for the selected dac output range. out min n code v fsr + v 2 ? ? 1 dac dac b uffer registe r (toggle reg b) dac a ctive registe r (toggle reg a) asynch ronous mode synchrono us mode (ldac (1) trigger) ser ial inte rface write dac rang e sele ct registe r 2.5v reference ref vcc v out toggl e vss gnd dac output (1) the da c trigger is g enerated by e ithe r b y writin g '1' to the ldac b it or by the / ldac p in in synchronou s mode. in a synchrono us mode, the da c latch is tran s pa rent.
24 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 9.3.1.2 dac register structure data written to the dac data registers is initially stored in the dac buffer registers. transfer of data from the dac buffer registers to the active dac registers can be configured to happen immediately (asynchronous mode) or initiated by a dac trigger signal (synchronous mode). once the dac active registers are updated, the dac outputs change to the new values. after a power-on or reset event, all dac registers are set to zero code, the dac output amplifiers are powered down, and the dac outputs are clamped to ground. 9.3.1.2.1 dac register synchronous and asynchronous updates the update mode for each dac channel is determined by the status of its corresponding sync-en bit. in asynchronous mode, a write to the dac data register results in an immediate update of the dac active register and dac output on a cs rising edge. in synchronous mode, writing to the dac data register doe not automatically update the dac output. instead the update occurs only after a trigger event. a dac trigger signal is generated either through the ldac bit or by the ldac pin. the synchronous update mode enables simultaneous update of multiple dac outputs. in both update modes a minimum wait time of 1 s is required between dac output updates. 9.3.1.2.2 broadcast dac register the dac broadcast register enables a simultaneous update of multiple dac outputs with the same value with a single register write. broadcast operation is only possible when all dac channels are in single-ended mode operation. if one or more outputs are configured in differential mode the broadcast command is ignored. each dac channel can be configured to update or remain unaffected by a broadcast command by setting the corresponding dac-brdcast-en bit. a register write to the brdcast-data register forces those dac channels that have been configured for broadcast operation to update their dac buffer registers to this value. the dac outputs update to the broadcast value according to their synchronous mode configuration. 9.3.1.2.3 clear dac operation the dac outputs are set in clear mode through the clear pin. in clear mode each dac data channel is set to the clear code associated with its configuration as shown in . a clr pin logic low forces all dac channels to clear the contents of their buffer and active registers to the clear code, and sets the analog outputs accordingly regardless of their synchronization setting. table 1. clear dac value unipolar / bipolar range differential mode clear code unipolar no zero code unipolar yes midscale code bipolar no midscale code bipolar yes midscale code when a dac is operating in toggle mode, a clear command sets both toggle registers to the clear value. 9.3.2 internal reference the dax1408 include a 2.5-v bandgap reference with a typical temperature drift of 5 ppm/ o c. the internal reference is externally available at the ref pin. an external buffer amplifier with a high impedance input is required to drive any external load. a minimum 150-nf capacitor is recommended between the reference output and gnd for noise filtering. a compensation capacitor (330 pf, typical) should be connected between the refcmp pin and refgnd. operation from an external reference is also supported by powering down the internal reference. the external reference is applied to the ref pin.
25 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.3.3 device reset options 9.3.3.1 power-on-reset (por) the dacx1408 includes a power-on reset function. after the supplies have been established, a por event is issued. the por causes all registers to initialize to their default values and communication with the device is valid only after a 1 ms power-on-reset delay. after a por event, the device is set in power-down mode where all dac channels and internal reference are powered down and the dac output pins are connected to ground through a 10-k internal resistor. 9.3.3.2 hardware reset a device hardware reset event is initiated by a minimum 500 ns logic low on the reset pin. a hardware reset initiates a por event. 9.3.3.3 software reset a device software reset event is initiated by writing the reserved code 0x1010 to soft-reset in the trigger register. the software reset command is triggered on the cs rising edge of the instruction. a software reset initiates a por event. 9.3.4 thermal protection due to the dacx1408 dac channel density and high drive capability it is important to understand the effects of power dissipation on the temperature of the device and ensure it does not exceed the maximum junction temperature. 9.3.4.1 analog temperature sensor: tempout pin the dacx1408 includes an analog temperature monitor with an unbuffered output voltage that is inversely proportional to the device junction temperature. the tempout pin output voltage has a temperature slope of -4 mv/ c and a 1.34-v offset as described by equation 2 . (2) where: ? t is the device junction temperature in c. ? v tempout is the temperature monitor output voltage. 9.3.4.2 thermal shutdown the dacx1408 incorporates a thermal shutdown that is triggered when the die temperature exceeds 140 o c. a thermal shutdown sets the temp-alm bit and causes all dac outputs to power-down, however the internal reference remains powered on. the almout pin can be configured to monitor a thermal shutdown condition by setting the tempalm-en bit. once a thermal shutdown is triggered, the device stays in shutdown even after the device temperature lowers. the die temperature must fall below 140 o c before the device can be returned to normal operation. to resume normal operation, the thermal alarm must be cleared through the alm-reset bit while the dac channels are in power-down mode. tempout -4 mv v t + 1.34 v c ? ? 1
26 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.4 device functional modes 9.4.1 toggle mode each dac in the device can be independently configured to operate in toggle mode. a dac channel in toggle mode incorporates two dac registers (register a and register b) and can be set to switch repetitively between these two values. the dacx1408 toggle mode operation can be configured to introduce a dither signal to the dac output, to generate a periodic signal or to implement on/off signaling, among some examples. to update the toggle registers the following sequence should be followed: 1. set dac channel in synchronous mode and disable toggle mode for that channel 2. write the desired register a value to the dac data register 3. issue a dac trigger signal to load register a 4. write the desired register b value to the dac data register 5. enable toggle mode to load register b once both registers are loaded with data, any of the three toggle[2:0] pins can be used to switch those dacs configured for toggle operation back and forth between the contents of their two dac specific registers by using an external clock or logic signal. a toggle pin logic low updates the dac output to the value set by register a. a logic high updates the dac output to the value set by register b. the three toggle[2:0] pins give the dacx1408 the option to operate with up to three toggle rates. additionally, the device can be configured for software controlled toggle operation by setting the softtoggle- en bit. in this mode, any of the three ab-tog[2:0] bits can be used as a toggle control signal. setting the abtog bit to 1 enables register b and clearing it to 0 enables register a. 9.4.2 differential mode each pair of dac channels in the device can be independently configured to operate as a differential output pair. the differential output of a dacx-y pair is updated by writing to the dacx channel. for proper operation, the two dac pairs must be configured to the same output range prior to enabling differential mode. figure 48 and figure 49 show the ideal differential output voltages (v diff ) and common mode voltages (v cm ) for a dac differential pair configured for 20-v and 0 to 40-v operation, respectively. once configured as a differential output, the dacx-y pair can be set for toggle operation by updating the dacx toggle registers as described in toggle mode . imbalances between the two differential signals result in common-mode and amplitude errors. the device incorporates an offset register that enables the user to introduce a voltage offset to the dacy channel of the dacx-y differential pair to compensate for a dc offset error between the two channels. the offset compensation gives a 0.2%fsr adjustment window. the differential dac data register must be rewritten after an update to the offset register. figure 48. differential bipolar output (16-bit): 20-v output range figure 49. differential unipolar output (16-bit): 0 to 40-v output range code dac output (v) 0 8192 16384 24576 32768 40960 49152 57344 65536 -40 -30 -20 -10 0 10 20 30 40 d046 dacx dacy v cm v diff code dac output (v) 0 8192 16384 24576 32768 40960 49152 57344 65536 -40 -30 -20 -10 0 10 20 30 40 d045 dacx dacy v cm v diff
27 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) 9.4.3 power-down mode the dacx1408 dac output amplifiers and internal reference power-down status can be individually configured and monitored though the pwdwn registers. setting a dac channel in power-down mode disables the output amplifier and clamps the output pin to ground through an internal 10-k resistor. the dac data registers are not cleared when the dac goes into power-down which makes it possible to have the same output voltage upon return to normal operation. the dac data registers can also be updated while in power-down mode. after a power-on or reset event all the dac channels and the internal reference are in power-down mode. the entire device can be configured into power-down or active modes through the dev-pwdwn bit.
28 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.5 programming the dacx1408 is controlled through a flexible four-wire serial interface that is compatible with spi type interfaces used on many microcontrollers and dsp controllers. the interface provides access to the dacx1408 registers and can be configured to daisy-chain multiple devices for write operations. the dacx1408 incorporates an optional error checking mode to validate spi data communication integrity in noisy environments. 9.5.1 stand-alone operation a serial interface access cycle is initiated by asserting the cs pin low. the serial clock sclk can be a continuous or gated clock. sdi data are clocked on sclk falling edges. a regular serial interface access cycle is 24 bits long with error checking disabled and 32 bits long with error checking enabled, thus the cs pin must stay low for at least 24 or 32 sclk falling edges. the access cycle ends when the cs pin is de-asserted high. if the access cycle contains less than then minimum clock edges, the communication is ignored. if the access cycle contains more than the minimum clock edges, only the first 24 or 32 bits are used by the device. when cs is high, the sclk and sdi signals are blocked and the sdo is in a hi-z state. in an error checking disabled access cycle (24 bits long) the first byte input to sdi is the instruction cycle which identifies the request as a read or write command and the 6-bit address to be accessed. the last 16 bits in the cycle form the data cycle. table 2. serial interface access cycle bit field description 23 rw identifies the communication as a read or write command to the address register. r/w = 0 sets a write operation. r/w = 1 sets a read operation. 22 x don't care bit. 21-16 a[5:0] register address. specifies the register to be accessed during the read or write operation. 15-0 di[15:0] data cycle bits. if a write command, the data cycle bits are the values to be written to the register with address a[5:0]. if a read command, the data cycle bits are don't care values. read operations require that the sdo pin is first enabled by setting the sdo-en bit. a read operation is initiated by issuing a read command access cycle. after the read command, a second access cycle must be issued to get the requested data. data are clocked out on sdo pin either on the falling edge or rising edge of sclk according to the fsdo bit. table 3. sdo output access cycle bit field description 23 rw echo rw from previous access cycle. 22 x echo bit 22 from previous access cycle. 21-16 a[5:0] echo address from previous access cycle. 15-0 do[15:0] readback data requested on previous access cycle.
29 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.5.1.1 streaming mode operation since updating the eight channels data registers requires a large amount of data to be passed to the device, the device supports streaming mode. in streaming mode the dac data registers can be written to the device without providing an instruction command for each data register. streaming mode is enabled by setting the stren bit. once enabled the streaming operation is implemented by holding the cs active and continuing to shift new data into the device. the instruction cycle includes the starting address. the device starts writing to this address and automatically increments the address as long as cs is asserted. if the last dac data register address has been reached and cs is still asserted, the additional data is ignored by the device. figure 50. serial interface streaming write cycle 9.5.2 daisy-chain operation for systems that contain more than one dacx1408 devices, the sdo pin can be used to daisy-chain them together. the sdo pin must be enabled by setting the sdo-en bit before initiating the daisy-chain operation. daisy-chain operation is useful in reducing the number of serial interface lines. the first falling edge on the cs pin starts the operation cycle. if more than 24 sclk pulses are applied while the cs pin is kept low, the data ripples out of the shift register and is clocked out on the sdo pin either on the falling edge or rising edge of sclk according to the fsdo bit. by connecting the sdo output of the first device to the sdi input of the next device in the chain, a multiple-device interface is constructed. each device in the system requires 24 clock pulses. as a result the total number of clock cycles must be equal to 24 n, where n is the total number of dacx1408 devices in the daisy chain. when the serial transfer to all devices is complete the cs signal is taken high. this action transfers the data from the spi shift registers to the internal registers of each device in the daisy chain and prevents any further data from being clocked into the input shift register. daisy- chain operation is not supported while in streaming mode. figure 51. daisy-chain layout 1 x w /cs sclk sdi sdo d15 d0 2 3 4 5 6 7 8 9 23 24 address n d15 d0 address n+1 25 39 40 d15 d0 address n+2 41 55 56 d15 d0 address n+3 57 71 72 stream write command a3 a2 a1 a0 a5 a4 sdi sdo sclk cs dacx1408 dacx1408 dacx1408 c b a sdi sdo sclk cs sdi sdo sclk cs
30 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.5.3 frame error checking if the dacx1408 is used in a noisy environment, error checking can be used to check the integrity of spi data communication between the device and the host processor. this feature is enabled by setting the crc-en bit. the error checking scheme is based on the crc-8-atm (hec) polynomial x 8 + x 2 + x + 1 (that is, 100000111). when error checking is enabled, the serial interface access cycle width is 32 bits. the normal 24-bit spi data is appended with an 8-bit crc polynomial by the host processor before feeding it to the device. in all serial interface readback operations the crc polynomial is output on the sdo pin as part of the 32-bit cycle. table 4. error checking serial interface access cycle bit field description 31 rw identifies the communication as a read or write command to the address register. r/w = 0 sets a write operation. r/w = 1 sets a read operation. 30 crc-error reserved bit. set to zero. 29-24 a[5:0] register address. specifies the register to be accessed during the read or write operation. 23-8 di[15:0] data cycle bits. if a write command, the data cycle bits are the values to be written to the register with address a[5:0]. if a read command, the data cycle bits are don't care values. 7-0 crc 8-bit crc polynomial. the dacx1408 decodes the 32-bit access cycle to compute the crc remainder on cs rising edges. if no error exists, the crc remainder is zero and data are accepted by the device. a write operation failing the crc check causes the data to be ignored by the device. after the write command, a second access cycle can be issued to determine the error checking results (crc-error bit) on the sdo pin. if there is a crc error, the crc-alm bit of the status register is set to 1. the almout pin can be configured to monitor a crc error by setting the crcalm-en bit. table 5. write operation error checking cycle bit field description 31 rw echo rw from previous access cycle (rw = 0). 30 crc-error returns a 1 when a crc error is detected, 0 otherwise. 29-24 a[5:0] echo address from previous access cycle. 23-8 do[15:0] echo data from previous access cycle. 7-0 crc calculated crc value of bits 31:8. a read operation must be followed by a second access cycle to get the requested data on the sdo pin. the error check result (crc-error bit) from the read command is output on the sdo pin. as in the case of a write operation failing the crc check, the crc-alm bit of the status register is set to 1 and the almout pin, if configured for crc alerts, is set low. table 6. read operation error checking cycle bit field description 31 rw echo rw from previous access cycle (rw = 1). 30 crc-error returns a 1 when a crc error is detected, 0 otherwise. 29-24 a[5:0] echo address from previous access cycle. 23-8 do[15:0] echo data from previous access cycle. 7-0 crc calculated crc value of bits 31:8.
31 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6 register maps table 7 lists the memory-mapped registers for the device. all register offset addresses not listed in table 7 should be considered as reserved locations and the register contents should not be modified. table 7. dacx1408 registers offset acronym register name section 00h nop nop register go 01h deviceid device id register go 02h status status register go 03h spiconfig spi configuration register go 04h genconfig general configuration register go 05h brdconfig broadcast configuration register go 06h syncconfig sync configuration register go 07h toggconfig0 dac[7:4] toggle configuration register go 08h toggconfig1 dac[3:0] toggle configuration register go 09h dacpwdwn dac power-down register go 0bh dacrange0 dac[7:4] range register go 0ch dacrange1 dac[3:0] range register go 0eh trigger trigger register go 0fh brdcast broadcast data register go 14h dac0 dac0 data register go 15h dac1 dac1 data register go 16h dac2 dac2 data register go 17h dac3 dac3 data register go 18h dac4 dac4 data register go 19h dac5 dac5 data register go 1ah dac6 dac6 data register go 1bh dac7 dac7 data register go 21h offset0 dac[6-7;4-5] differential offset register go 22h offset1 dac[2-3;0-1] differential offset register go
32 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated complex bit access types are encoded to fit into small table cells. table 8 shows the codes that are used for access types in this section. table 8. access type codes access type code description read type r r read write type w w write reset or default value - n value after reset or the default value register array variables i,j,k,l,m,n when these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. the register groups form a hierarchical structure and the array is represented with a formula. y when this variable is used in a register name, an offset, or an address it refers to the value of a register array.
33 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.1 nop register (offset = 00h) [reset = 0000h] nop is shown in figure 52 and described in table 9 . return to summary table . figure 52. nop register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nop w-0h table 9. nop register field descriptions bit field type reset description 15-0 nop w 0h no operation. write 0000h for proper no-operation command. 9.6.2 deviceid register (offset = 01h) [reset = ----h] deviceid is shown in figure 53 and described in table 10 . return to summary table . figure 53. deviceid register 15 14 13 12 11 10 9 8 deviceid r----h 7 6 5 4 3 2 1 0 deviceid versionid r----h r-0h table 10. deviceid register field descriptions bit field type reset description 15-2 deviceid r ---h device id dac81408: 298h dac71408: 288h dac61408: 248h 1-0 versionid r 0h version id. subject to change.
34 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.3 status register (offset = 02h) [reset = 0000h] status is shown in figure 54 and described in table 11 . return to summary table . figure 54. status register 15 14 13 12 11 10 9 8 reserved r-0h 7 6 5 4 3 2 1 0 reserved crc-alm dac-busy temp-alm r-0h r-0h r-0h r-0h table 11. status register field descriptions bit field type reset description 15-3 reserved r 0h this bit is reserved. 2 crc-alm r 0h crc-alm = 1 indicates a crc error. 1 dac-busy r 0h dac-busy = 1 indicates dac registers are not ready for updates. 0 temp-alm r 0h temp-alm = 1 indicates die temperature is over +140 c. a thermal alarm event forces the dac outputs to go into power-down mode.
35 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.4 spiconfig register (offset = 03h) [reset = 0a24h] spiconfig is shown in figure 55 and described in table 12 . return to summary table . figure 55. spiconfig register 15 14 13 12 11 10 9 8 reserved tempalm-en dacbusy-en crcalm-en reserved r-0h r/w-1h r/w-0h r/w-1h r-0h 7 6 5 4 3 2 1 0 reserved softtoggle -en dev-pwdwn crc-en str-en sdo-en fsdo reserved r-1h r/w-0h r/w-1h r/w-0h r/w-0h r/w-1h r/w-0h r-0h table 12. spiconfig register field descriptions bit field type reset description 15-12 reserved r 0h this bit is reserved. 11 tempalm-en r/w 1h when set to 1 a thermal alarm triggers the almout pin. 10 dacbusy-en r/w 0h when set to 1 the almout pin is set between dac output updates. contrary to other alarm events, this alarm resets automatically. 9 crcalm-en r/w 1h when set to 1 a crc error triggers the almout pin. 8 reserved r 0h this bit is reserved. 7 reserved r 1h this bit is reserved. 6 softtoggle-en r/w 0h when set to 1 enables soft toggle operation. 5 dev-pwdwn r/w 1h dev-pwdwn = 1 sets the device in power-down mode dev-pwdwn = 0 sets the device in active mode 4 crc-en r/w 0h when set to 1 frame error checking is enabled. 3 str-en r/w 0h when set to 1 streaming mode operation is enabled. 2 sdo-en r/w 1h when set to 1 the sdo pin is operational. 1 fsdo r/w 0h fast sdo bit (half-cycle speedup). when 0, sdo updates during sclk rising edges. when 1, sdo updates during sclk falling edges. 0 reserved r 0h this bit is reserved.
36 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.5 genconfig register (offset = 04h) [reset = 7f00h] genconfig is shown in figure 56 and described in table 13 . return to summary table . figure 56. genconfig register 15 14 13 12 11 10 9 8 reserved ref-pwdwn reserved r-0h r/w-1h r-1h 7 6 5 4 3 2 1 0 reserved reserved dac-6-7-diff- en dac-4-5-diff- en dac-2-3-diff- en dac-0-1-diff- en reserved reserved r-0h r-0h r/w-0h r/w-0h r/w-0h r/w-0h r-0h r-0h table 13. genconfig register field descriptions bit field type reset description 15 reserved r 0h this bit is reserved. 14 ref-pwdwn r/w 1h ref-pwdwn = 1 powers down the internal reference ref-pwdwn = 0 activates the internal reference 13-8 reserved r 1h this bit is reserved. 7 reserved r 0h this bit is reserved. 6 reserved r 0h this bit is reserved. 5 dac-6-7-diff-en r/w 0h when set to 1 the corresponding dac pair is set to operate in differential mode. the dac data registers must be rewritten after enabling or disabling differential operation. 4 dac-4-5-diff-en r/w 0h 3 dac-2-3-diff-en r/w 0h 2 dac-0-1-diff-en r/w 0h 1 reserved r 0h this bit is reserved. 0 reserved r 0h this bit is reserved.
37 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.6 brdconfig register (offset = 05h) [reset = ffffh] brdconfig is shown in figure 57 and described in table 14 . return to summary table . figure 57. brdconfig register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved dac7- brdcast-en dac6- brdcast-en dac5- brdcast-en dac4- brdcast-en r-1h r-1h r-1h r-1h r/w-1h r/w-1h r/w-1h r/w-1h 7 6 5 4 3 2 1 0 dac3- brdcast-en dac2- brdcast-en dac1- brdcast-en dac0- brdcast-en reserved reserved reserved reserved r/w-1h r/w-0h r/w-0h r/w-0h r-1h r-1h r-1h r-1h table 14. brdconfig register field descriptions bit field type reset description 15 reserved r 1h this bit is reserved. 14 reserved r 1h this bit is reserved. 13 reserved r 1h this bit is reserved. 12 reserved r 1h this bit is reserved. 11 dac7-brdcast-en r/w 1h when set to 1 the corresponding dac is set to update its output to the value set in the brdcast register. all dac channels must be configured in single-ended mode for broadcast operation. if one or more outputs are configured in differential mode the broadcast mode is ignored. when cleared to 0 the corresponding dac output remains unaffected by a brdcast command. 10 dac6-brdcast-en r/w 1h 9 dac5-brdcast-en r/w 1h 8 dac4-brdcast-en r/w 1h 7 dac3-brdcast-en r/w 1h 6 dac2-brdcast-en r/w 1h 5 dac1-brdcast-en r/w 1h 4 dac0-brdcast-en r/w 1h 3 reserved r 1h this bit is reserved. 2 reserved r 1h this bit is reserved. 1 reserved r 1h this bit is reserved. 0 reserved r 1h this bit is reserved.
38 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.7 syncconfig register (offset = 06h) [reset = 0000h] syncconfig is shown in figure 58 and described in table 15 . return to summary table . figure 58. syncconfig register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved dac7-sync- en dac6-sync- en dac5-sync- en dac4-sync- en r-0h r-0h r-0h r-0h r/w-0h r/w-0h r/w-0h r/w-0h 7 6 5 4 3 2 1 0 dac3-sync- en dac2-sync- en dac1-sync- en dac0-sync- en reserved reserved reserved reserved r/w-0h r/w-0h r/w-0h r/w-0h r-0h r-0h r-0h r-0h table 15. syncconfig register field descriptions bit field type reset description 15 reserved r 0h this bit is reserved. 14 reserved r 0h this bit is reserved. 13 reserved r 0h this bit is reserved. 12 reserved r 0h this bit is reserved. 11 dac7-sync-en r/w 0h when set to 1 the corresponding dac output is set to update in response to an ldac trigger (synchronous mode). when cleared to 0 the corresponding dac output is set to update immediately (asynchronous mode). 10 dac6-sync-en r/w 0h 9 dac5-sync-en r/w 0h 8 dac4-sync-en r/w 0h 7 dac3-sync-en r/w 0h 6 dac2-sync-en r/w 0h 5 dac1-sync-en r/w 0h 4 dac0-sync-en r/w 0h 3 reserved r 0h this bit is reserved. 2 reserved r 0h this bit is reserved. 1 reserved r 0h this bit is reserved. 0 reserved r 0h this bit is reserved.
39 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.8 toggconfig0 register (offset = 07h) [reset = 0000h] toggconfig0 is shown in figure 59 and described in table 16 . return to summary table . figure 59. toggconfig0 register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved r-0h r-0h r-0h r-0h 7 6 5 4 3 2 1 0 dac7-ab-togg-en dac6-ab-togg-en dac5-ab-togg-en dac4-ab-togg-en r/w-0h r/w-0h r/w-0h r/w-0h table 16. toggconfig0 register field descriptions bit field type reset description 15-14 reserved r 0h this bit is reserved. 13-12 reserved r 0h this bit is reserved. 11-10 reserved r 0h this bit is reserved. 9-8 reserved r 0h this bit is reserved. 7-6 dac7-ab-togg-en r/w 0h enables toggle mode operation and configures the toggle pin or soft toggle bit: 0h = toggle mode disabled 1h = toggle mode enabled: toggle0 2h = toggle mode enabled: toggle1 3h = toggle mode enabled: toggle2 5-4 dac6-ab-togg-en r/w 0h 3-2 dac5-ab-togg-en r/w 0h 1-0 dac4-ab-togg-en r/w 0h
40 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.9 toggconfig1 register (offset = 08h) [reset = 0000h] toggconfig1 is shown in figure 60 and described in table 17 . return to summary table . figure 60. toggconfig1 register 15 14 13 12 11 10 9 8 dac3-ab-togg-en dac2-ab-togg-en dac1-ab-togg-en dac0-ab-togg-en r/w-0h r/w-0h r/w-0h r/w-0h 7 6 5 4 3 2 1 0 reserved reserved reserved reserved r-0h r-0h r-0h r-0h table 17. toggconfig1 register field descriptions bit field type reset description 15-14 dac3-ab-togg-en r/w 0h enables toggle mode operation and configures the toggle pin or soft toggle bit: 0h = toggle mode disabled 1h = toggle mode enabled: toggle0 2h = toggle mode enabled: toggle1 3h = toggle mode enabled: toggle2 13-12 dac2-ab-togg-en r/w 0h 11-10 dac1-ab-togg-en r/w 0h 9-8 dac0-ab-togg-en r/w 0h 7-6 reserved r 0h this bit is reserved. 5-4 reserved r 0h this bit is reserved. 3-2 reserved r 0h this bit is reserved. 1-0 reserved r 0h this bit is reserved.
41 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.10 dacpwdwn register (offset = 09h) [reset = ffffh] dacpwdwn is shown in figure 61 and described in table 18 . return to summary table . figure 61. dacpwdwn register 15 14 13 12 11 10 9 8 reserved reserved reserved reserved dac7-pwdwn dac6-pwdwn dac5-pwdwn dac4-pwdwn r-1h r-1h r-1h r-1h r/w-1h r/w-1h r/w-1h r/w-1h 7 6 5 4 3 2 1 0 dac3-pwdwn dac2-pwdwn dac1-pwdwn dac0-pwdwn reserved reserved reserved reserved r/w-1h r/w-1h r/w-1h r/w-1h r-1h r-1h r-1h r-1h table 18. dacpwdwn register field descriptions bit field type reset description 15 reserved r 1h this bit is reserved. 14 reserved r 1h this bit is reserved. 13 reserved r 1h this bit is reserved. 12 reserved r 1h this bit is reserved. 11 dac7-pwdwn r/w 1h when set to 1 the corresponding dac is in power-down mode and its output is connected to gnd through a 10-k internal resistor. 10 dac6-pwdwn r/w 1h 9 dac5-pwdwn r/w 1h 8 dac4-pwdwn r/w 1h 7 dac3-pwdwn r/w 1h 6 dac2-pwdwn r/w 1h 5 dac1-pwdwn r/w 1h 4 dac0-pwdwn r/w 1h 3 reserved r 1h this bit is reserved. 2 reserved r 1h this bit is reserved. 1 reserved r 1h this bit is reserved. 0 reserved r 1h this bit is reserved.
42 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.11 dacrangen register (offset = 0bh - 0ch) [reset = 0000h] dacrangen is shown in figure 62 and described in table 19 . return to summary table . figure 62. dacrangen register 15 14 13 12 11 10 9 8 daca-range[3:0] dacb-range[3:0] w-0h w-0h 7 6 5 4 3 2 1 0 dacc-range[3:0] dacd-range[3:0] w-0h w-0h table 19. dacrangen register field descriptions bit field type reset description 15-12 daca-range[3:0] w 0h sets the output range for the corresponding dac. 0000 = 0 to 5 v 0001 = 0 to 10 v 0010 = 0 to 20 v 0100 = 0 to 40 v 1001 = -5 v to +5 v 1010 = -10 v to +10 v 1100 = -20 v to +20 v 1110 = -2.5 v to +2.5 v all others: invalid the two outputs of a differential dac pair must be configured to the same output range prior to setting them up as a differential pair. a: 7 or 3; b: 6 or 2; c: 5 or 1; d: 4 or 0 11-8 dacb-range[3:0] w 0h 7-4 dacc-range[3:0] w 0h 3-0 dacd-range[3:0] w 0h
43 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.12 trigger register (offset = 0eh) [reset = 0000h] trigger is shown in figure 63 and described in table 20 . return to summary table . figure 63. trigger register 15 14 13 12 11 10 9 8 reserved alm-reset w-0h w-0h 7 6 5 4 3 2 1 0 ab-tog2 ab-tog1 ab-tog0 ldac soft-reset[3:0] w-0h w-0h w-0h w-0h w-0h table 20. trigger register field descriptions bit field type reset description 15-9 reserved w 0h this bit is reserved 8 alm-reset w 0h set this bit to 1 to clear an alarm event. not applicable for a dac- busy alarm event. 7 ab-tog2 w 0h if soft toggle is enabled set, this bit controls the toggle between values for those dacs that have been set in toggle mode 2 in the toggconfig register. set to 1 to update to register b and clear to 0 for register a. 6 ab-tog1 w 0h if soft toggle is enabled set, this bit controls the toggle between values for those dacs that have been set in toggle mode 1 in the toggconfig register. set to 1 to updated to register b and clear to 0 for register a. 5 ab-tog0 w 0h if soft toggle is enabled set, this bit controls the toggle between values for those dacs that have been set in toggle mode 0 in the toggconfig register. set to 1 to update to register b and clear to 0 for register a. 4 ldac w 0h set this bit to 1 to synchronously load those dacs who have been set in synchronous mode in the syncconfig register. 3-0 soft-reset[3:0] w 0h when set to the reserved code 1010 resets the device to its default state.
44 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.13 brdcast register (offset = 0fh) [reset = 0000h] brdcast is shown in figure 64 and described in table 21 . return to summary table . figure 64. brdcast register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 brdcast-data[15:0] r/w-0h table 21. brdcast register field descriptions bit field type reset description 15-0 brdcast-data[15:0] r/w 0h writing to the brdcast register forces those dac channels that have been set to broadcast in the brdconfig register to update its active register data to the brdcast-data one. data is msb aligned in straight binary format and follows the format below: dac81408: { data[15:0] } dac71408: { data[13:0], x, x } dac61408: { data[11:0], x, x, x, x} x ? don 't care bits 9.6.14 dacn register (offset = 14h - 1bh) [reset = 0000h] dacn is shown in figure 65 and described in table 22 . return to summary table . figure 65. dacn register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dacn-data[15:0] r/w-0h table 22. dacn register field descriptions bit field type reset description 15-0 dacn-data[15:0] r/w 0h stores the 16-, 14- or 12-bit data to be loaded to dacn in msb aligned straight binary format. in differential dac mode data is loaded into the lowest-valued dac in the dac pair (in pair dac 01, data is loaded into dac0 and writes to dac1 are ignored). data follows the format below: dac81408: { data[15:0] } dac71408: { data[13:0], x, x } dac61408: { data[11:0], x, x, x, x} x ? don 't care bits
45 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.6.15 offsetn register (offset = 21h - 22h) [reset = 0000h] offsetn is shown in figure 66 and described in table 23 . return to summary table . figure 66. offsetn register 15 14 13 12 11 10 9 8 offsetab[7:0] r/w-0h 7 6 5 4 3 2 1 0 offsetcd[7:0] r/w-0h table 23. offsetn register field descriptions bit field type reset description 15-8 offsetab[7:0] r/w 0h provides offset adjustment to dacy in the differential dacx-y pair in two 's complement format. data follows the format below: ? dac81408: ? format: { offset[7:0] } ? range: -128 lsb to +127 lsb ? dac71408: ? format: { offset[5:0], x, x } ? range: -32 lsb to +31 lsb ? dac61408: ? format: { offset[3:0], x, x, x, x} ? range: -8 lsb to +7 lsb x ? don 't care bits the differential dac data register must be rewritten after updating the offset register. ab: 6-7 or 2-3; cd: 4-5 or 0-1 7-0 offsetcd[7:0] r/w 0h
46 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 10 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 10.1 application information the dacx1408 family provides 8-channel high-voltage and high-current output in both single-ended and differential configurations. the outputs can be configured to multiple ranges and square waves can be generated using the toggle modes. this makes the dac family suitable for automatic test equipment (ate) and servo control applications. in addition to these features, the low power-on glitch of this dac makes it suitable for motor control applications like cnc machines as well. 10.2 typical application figure 67. schematic for remote ground tracking 10.2.1 design requirements in ate and motor control applications, typically the systems are designed modular wherein the control module is located spatially away from the device under test (dut) module. such a scheme allows ground potentials across modules to vary due to the impedance of the interconnects. this ground potential variation, in turn introduces inaccuracies to the dac output when measured with respect to the remote or dut ground. figure 67 provides a method to compensate the variations in the remote ground. the ground variation in such applications is typically within 300 mv that includes dc and 50 hz/60 hz mains frequency components. while the best way to handle this variation is to put opamps in level shifter configuration at each output, a low cost and low footprint solution is always preferable. the following sections focus on the latter approach.
47 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) 10.2.2 detailed design procedure for remote ground tracking in order to make the dac outputs follow the remote ground, the best approach is to level shift the reference input. figure 67 depicts a method wherein both the ref and refgnd inputs are level shifted with respect to dutgnd. however, as the dac doesn ? t allow the refgnd to become negative compared to gnd, an offset voltage of 300mv needs to be applied as shown. this method requires an external 2.5v reference and a way to generate a stable 300-mv reference. a dual opamp u1 is used to shift both refgnd and ref by (dutgnd + 300-mv offset). table 24 provides the nodal analysis of the circuit. as evident, the dac outputs track the dutgnd with an offset of 300mv. this offset can be easily compensated in software. note that the absolute max values between refgnd and gnd must be respected. when the absolute max values are reached, they should only be for a transient period and not for sustained amount of time. table 24. nodal analysis of the circuit dutgnd (gnd 0.3v) refgnd pin ref pin vout-gnd at 0v code vout-gnd at 5v code vout-dutgnd at 0v code vout-dutgnd at 5v code 0v 0.3v 2.8v 0.3v 5.3v 0.3v 5.3v 0.3v 0.6v 3.1v 0.6v 5.6v 0.3v 5.3v -0.3v 0v 2.5v 0v 5v 0.3v 5.3v 10.2.2.1 generating 300mv offset there is no off-the-shelf solution for generating a 300-mv offset, unfortunately. figure 67 depicts a method to generate it using discrete components. it uses lm4041 adjustable shunt regulator on high-side from the 2.5-v reference. it has a reference input pin that sets the voltage across this device. given that v ref is 1.233 v, choosing r1 = 16 k ? and r2 = 12 k ? the voltage v o can be calculated by superposition as 2.16 v. this will provide an offset of (2.5 v ? 2.16 v) = 340 mv that will provide a safe margin from dac ground. 10.2.2.2 amplifier selection the amplifier needs to be bipolar in order to operate linearly near ground. a dual package is preferable for optimizing area. considering these factors, tlv2442a seems to be the best option from cost and accuracy points of view. other parts like opa2277 can be used when higher accuracy is required. 10.2.2.3 passive component selection in order to minimize additional offset and gain error the gain resistors around the opamps need to be matched. an 8-channel resistor network can be used for better matching. r c and c c values can be chosen as 22 ? and 1000 pf, respectively in order to compensate the pole caused by the large bypass capacitor at the opamp outputs.
48 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 10.2.3 application curves figure 68. power-on glitch with dutgnd compensation figure 69. inl (major code) at different values of dutgnd
49 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 power supply recommendations the dacx1408 requires 5 power supply inputs: vio, vdd, vaa, vcc and vss. vdd and vaa should be at same level. assuming vio and vdd/vaa to be different, there are 4 separate power supply sources required. it is recommended to provide a 0.1- f ceramic capacitor close to each power supply pin. please note that vcc and vss have 2 pins each. in addition, a 4.7- f or 10- f bulk capacitor is recommended for each power supply. tantalum or aluminum types can be chosen for the bulk capacitors. there is no sequencing requirement for the power supplies. as the dac output range is configurable, the power supply headroom should be taken care of for achieving linearity at codes close to power supply rails. when sourcing or sinking current from or to the dac output, the heat dissipation needs to be considered. for example, a typical application of mzm bias with 25-ma load current from or to 12 channels with 2.5-v power supply headroom can create a power dissipation across the dac of (12*2.5*25 ma) = 0.75 w. the thermal design to dissipate this much of power may involve inclusion of heat sinks in order to avoid thermal shutdown of the device.
50 dac81408 , dac71408 , dac61408 slaser3a ? july 2018 ? revised november 2018 www.ti.com product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 layout 12.1 layout guidelines the pin out of dacx1408 has been designed in such a way that the analog, digital and power pins are spatially separated from each other, which makes the pcb layout simple. an example layout is shown in figure 70 . as evident, every power supply pin has a 0.1- f capacitor close to it. the layout of the analog and digital signals should be laid out away from each other or on different pcb layers. it is recommended to provide an unbroken reference plane (either ground or vio) for the digital signals. the higher frequency signals such as sclk and sdi should have appropriate impedance termination in order to address signal integrity. 12.2 layout example figure 70. example layout
51 dac81408 , dac71408 , dac61408 www.ti.com slaser3a ? july 2018 ? revised november 2018 product folder links: dac81408 dac71408 dac61408 submit documentation feedback copyright ? 2018, texas instruments incorporated 13 device and documentation support 13.1 documentation support 13.2 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 25. related links parts product folder order now technical documents tools & software support & community dac81408 click here click here click here click here click here dac71408 click here click here click here click here click here dac61408 click here click here click here click here click here 13.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 13.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 13.5 trademarks e2e is a trademark of texas instruments. 13.6 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 14 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 30-nov-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples dac61408rhar preview vqfn rha 40 2500 tbd call ti call ti -40 to 125 dac61408rhat preview vqfn rha 40 250 tbd call ti call ti -40 to 125 DAC71408RHAR preview vqfn rha 40 2500 tbd call ti call ti -40 to 125 dac71408rhat preview vqfn rha 40 250 tbd call ti call ti -40 to 125 dac81408rhar preview vqfn rha 40 2500 tbd call ti call ti -40 to 125 dac81408rhat preview vqfn rha 40 250 tbd call ti call ti -40 to 125 pdac8e08rhat active vqfn rha 40 250 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 30-nov-2018 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ? as is ? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti ? s products are provided subject to ti ? s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti ? s provision of these resources does not expand or otherwise alter ti ? s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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